The present invention relates to a display device, signal line driver, and data transfer method, and relates in particular to technology for generating and transferring control signals in display devices.
Increasingly large-sized panel display devices and larger data transfer quantities due to improved panel picture image resolution cause problems in methods for transferring data to drivers to drive display devices. In liquid crystal display devices for example, the data transfer technology for supplying video data from the timing controller to the data driver (or signal line driver, source driver) for driving the data lines (signal lines) in the liquid crystal display panel becomes a problem.
Under these circumstances the problem is especially serious when driving large-sized display panels. Large-size display panels contain multiple data drivers for driving the data lines. Currently made large-size display devices contain a common bus to reduce the number of wires and in many cases the applicable common bus transfers the video data successively to the data drivers, however this type of arrangement has the problem of requiring an excessively large data transfer rate. More specifically, the allowable time for sending this video data to a single data driver when setting the horizontal synchronization time length as TH, and the number of data drivers as N, is TH/N. Increasing the number of data drivers to cope with large-sized display devices and better panel resolution therefore signifies that the allowable time for sending video data to a single data driver becomes ever shorter.
One technique for resolving this type of problem is transferring the video data point-to-point to the respective plural data drivers. FIG. 1 is a block diagram showing one example of a configuration in a large-size liquid crystal display device for transferring video data by the point-to-point technique to the data drivers. The technology for the structure in FIG. 1 is disclosed in Japanese Unexamined Patent Application Publication No. 2000-155552. The liquid crystal display device 110 in FIG. 1 includes a signal processor circuit 120, a liquid crystal panel 130, source drivers 202-216, and gate drivers 402-408. Separate lines supply the video data to the respective source drivers 202-216.
In the liquid crystal display device 110 in FIG. 1, the signal processor circuit 120 supplies gate driver clock GCLK to the respective gate drivers 402-408, while gate driver start pulses GSP on the other hand are supplied only to the gate drivers 402 positioned on the ends. After a specified time has elapsed after receiving a gate driver start pulse GSP from the signal processor circuit 120, the gate driver 402 supplies a gate driver start pulse to the gate driver 404. The gate drivers 406 and 408 receive a gate driver start pulse from the adjacent gate drivers 404, 406 in the same way.
The technique for transferring video data point-to-point to the respective plural data drivers alleviates restrictions on the data transfer rate but causes the problem of requiring a larger number of wires coupled to applicable devices and a larger number of output pins on the device (typically a timing controller) that supplies video data to each data driver. The liquid crystal display device in FIG. 1 lowers the number of required wires and output pins by using serial data transfer but the number of output pins and wires should preferably be kept as small as possible in view of the need to lower costs and simplify the equipment.
One technique for reducing the number of output pins and wiring couplings on the timing controller utilizes multiplexed signals as control signals for data driver control in video data signals used to transfer video data. One data transfer method for example utilizes clock signals generated from video data CDR (clock data recovery) to send video data to data drivers and send the video data and clock signals along the same wire and so is effective in reducing the number of wires. This technique is disclosed in Japanese Unexamined Patent Application Publication No. 2009-204677 and by K. Yamaguchi et al. in “A 2.0 Gb/s Clock-Embedded Interface for full-HD 10b 120 Hz LCD drivers with ⅕-Rate Noise Tolerant Phase and Frequency Recovery,” 2009 IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 192-193, February, 2009.